The increasingly higher integration of semiconductor integrated circuits in recent years has led to higher density in wiring patterns and, in turn, an increase in a parasitic capacitance generated between wires. Since such an increase in the parasitic capacitance causes signal wiring delay, reducing the inter-wiring parasitic capacitance is an important issue in semiconductor integrated circuits that must be operated at high speed. Currently, reduction in the inter-wiring parasitic capacitance is realized by reducing the relative permittivity between wires and of interlayer insulation films.
Conventionally, a silicon dioxide film (SiO2) (relative permittivity of substantially 3.9 to 4.2) or a SiO2 film containing fluorine (F) (relative permittivity of substantially 3.5 to 3.8) has been frequently used as an inter-wiring insulation film. Additionally, in some semiconductor integrated circuits, a carbon-containing silicon oxide film (SiOC) (relative permittivity of substantially 3.0) whose relative permittivity is lower than the conventional SiO2 film is used as an inter-wiring insulation film. Furthermore, more recently, for the purpose of further reducing the inter-wiring parasitic capacitance, a semiconductor device is proposed which uses a low-permittivity film made up of a porous carbon-containing silicon oxide film (porous SiOC) (relative permittivity of substantially 2.5 to 3.0) with a relative permittivity of substantially 3.0 or lower as an inter-wiring insulation film.
However, when using a low-permittivity film made up of SiOC or porous SiOC as an insulation film between wires, the high proportion of Si—CH3 bonds/Si—O bonds in the film causes the Si—CH3 bonds to be separated by plasma processing performed during a barrier metal film formation process or the like, resulting in an increase in high-dielectric Si—O bonds. As a result, the relative permittivity of the SiOC film disadvantageously increases.
In order to eliminate this disadvantage, methods are proposed in which a protective film (pore-seal film) (relative permittivity of substantially 4.7 or higher) whose Si—CH3 bonds are less likely to be separated by plasma processing than a SiOC film is formed on a SiOC film (for example, refer to Japanese Patent Laid-Open No. 2007-027347).
FIG. 1 shows an example of a wiring structure in a semiconductor device using a general SiOC film as an insulation film between wires. A first metallic wire 2 is formed on a first insulation film 1 made up of a SiO2 film formed on top of a substrate (not shown) composed of silicon by a barrier metal film 2a composed of tantalum nitride (TaN) and a conductive film 2b composed of copper (Cu). A second insulation film 3 composed of silicon carbide (SiC) and which functions as an anti-metallic diffusion film is formed on top of the first insulation film 1 so as to cover the first metallic wire 2. A third insulation film 4 composed of low-permittivity SiOC is formed on top of the second insulation film 3. Furthermore, a fourth insulation film 5 composed of SiO2 is formed on the third insulation film 4.
In this case, a second metallic wire 7 is formed on the third insulation film 4 and the fourth insulation film 5 by a pore seal film 6 composed of SiCN, a barrier metal film 7a composed of TaN and a conductive film 7b composed of Cu. In addition, a via 8 that electrically connects the first metallic wire 2 and the second metallic wire 7 is formed on the second insulation film 3 and the third insulation film 4.
Next, a method of manufacturing a semiconductor device that uses a SiOC film as an insulation film between wires will be described.
FIGS. 2A to 2F show a cross-sectional state of each process in a conventional method of manufacturing a semiconductor device in the sequence of processes.
First, as shown in FIG. 2A, a metallic wiring groove pattern is formed by a photolithographic method over the first insulation film 1 composed of SiO2 and formed on top of a substrate (not shown). Subsequently, dry etching is performed on the metallic wiring groove pattern to form a wiring groove on the insulation film 1. Next, after depositing the barrier metal film 2a composed of TaN and the conductive film 2b composed of Cu so as to embed the wiring groove, excess Cu is removed by a chemical mechanical polishing (CMP) method to form the first metallic wire 2.
Next, as shown in FIG. 2B, the second insulation film 3 composed of SiC is deposited substantially 50 nm on top of the first insulation film 1 so as to cover the first metallic wire 2. The low-permittivity third insulation film 4 composed of SiOC is then deposited substantially 500 nm on top of the second insulation film 3. Subsequently, the fourth insulation film 5 composed of SiO2 is deposited substantially 50 nm on top of the third insulation film 4 by a plasma CVD method.
Next, as shown in FIG. 2C, after forming a via hole pattern on top of the fourth insulation film 5 by photolithography, the second insulation film 3, the third insulation film 4 and the fourth insulation film 5 are selectively dry-etched to form a via hole 8a that exposes an upper face of the first metallic wire 2.
Next, as shown in FIG. 2D, after forming a mask on top of the fourth insulation film 5, the third insulation film 4 and the fourth insulation film 5 are selectively dry-etched to form a wiring groove 7c having a desired pattern and depth.
Next, as shown in FIG. 2E, the pore seal film 6 is formed on lateral faces and bottom faces of the wiring groove 7c and the via hole 8a and on the entire upper face of the fourth insulation film 5. Subsequently, the pore seal film 6 on the bottom face of the via hole 8a is removed by Ar-resputtering.
Next, as shown in FIG. 2F, the barrier metal film 7a is deposited on wall faces and bottom faces of the wiring groove 7c and the via hole 8a. Subsequently, the barrier metal film on the bottom face of the via hole is removed by Ar-resputtering. A barrier metal film is then once again formed by sputtering. Subsequently, the conductive film 7b is deposited on the wiring groove 7c and the via hole 8a. Excess conductive film, barrier metal film and pore seal film outside of the wiring groove 7c is then removed by a CMP method to form the second metallic wire 7 and the via B.
In the process shown in FIG. 2F, the pore seal film 6 functions so as to block plasma exposure of the third insulation film 4 during the formation of the barrier metal film 7a. 
However, with the conventional semiconductor device and the method of manufacturing the same described above, although plasma exposure of the third insulation film can be blocked by the pore seal film, the high relative permittivity of the pore seal film such as a SiCN film gives rise to an increase in the effective permittivity between interlayer insulation films in a wiring layer. As a result, signal delay on the wiring increases.
In addition, since the pore seal film contains Si—CH3 bonds and is therefore vulnerable to plasma processing, the Si—CH3 bonds in the low-permittivity film on the wall faces and bottom faces of the wiring groove and the via hole are separated by plasma processing applied to the wiring groove and the via hole during the barrier metal film formation process or the like. As a result, relative permittivity increases which, in turn, causes degradation of signal delay characteristics on the wiring.